Byte order is arrangement of data in terms of bytes and is conventionally prescribed as specifications of a processor and a data format when the processor handles multiple bytes. The byte order is broadly classified into little endian and big endian. The little endian is the arrangement in which bytes are stored in the order from the least significant byte. The big endian is the arrangement in which bytes are stored in the order from the most significant byte.
If byte order specification of a processor is different from data format specification, when processing corresponding data, the processor rearranges the data in terms of bytes. The rearrangement in terms of bytes is referred to as endian conversion.
For example, a technique is disclosed that, when an apparatus transmits/receives data with respect to another apparatus having byte order different from the apparatus, that apparatus transmits the data after software swaps the data or swaps received data before reading the data (hereinafter referred to as a conventional technique 1).
A technique of performing the endian conversion is disclosed as a technique of performing the endian conversion within a processor (see, e.g., Japanese Laid-Open Patent Publication Nos. H8-278918 and 2007-34680). A technique of performing the endian conversion by other hardware is disclosed as a technique of performing the endian conversion with a bus having a swap circuit (see, e.g., Japanese Laid-Open Patent Publication No. 2000-305892).
However, in the conventional techniques described above, the technique according to the conventional technique 1 uses conversion by software and therefore has a problem of deterioration in processing performance. Although the techniques according to Japanese Laid-Open Patent Publication Nos. H8-278918 and 2007-34680 enables high-speed processing because hardware can be used, a processor operates at high speed and therefore, if an endian conversion mechanism is added, it is problematically difficult to maintain the processing performance of the processor. Although the technique according to Japanese Laid-Open Patent Publication No. 2000-305892 enables endian conversion of entire bus width, it is difficult to perform the endian conversion with a complicated data structure such as performing the endian conversion for a portion of an address range within the bus width.